As shown in FIG. 1, a prior art switching power source device of resonance type comprises a DC power source 1; first and second MOS-FETs 3 and 4 as first and second switching elements connected in series to DC power source 1; a series circuit which includes a resonance reactor or choke coil 7, a primary winding 9a of a transformer 9 and a capacitor 8 connected in series to each other and to two junctions between first and second MOS-FETs 3 and 4 and between second MOS-FET 4 and power source 1; a rectifying smoother 17 connected to secondary windings 9b and 9c of transformer 9 to supply DC power to a load 13; an output voltage detector 18 for detecting an output voltage applied on load 13; and a control circuit 2 for applying on-off signals Vg1, Vg2 to each control or gate terminal of first and second MOS-FETs 3 and 4. A voltage resonance capacitor 6 is connected in parallel to second MOS-FET 4. Parasitic diodes 3a and 4a are connected between drain and source terminals of first and second MOS-FETs 3 and 4.
Secondary windings 9b and 9c of transformer 9 comprise a first secondary winding 9b; a second secondary winding 9c connected in series to first secondary winding 9b. Each distal end of first and second secondary windings 9b and 9c is connected to a positive terminal of load 13 through respectively diodes 10 and 11. Each mesial end of first and second secondary windings 9b and 9c is connected to a center tap to a negative terminal of load 13 which is connected in parallel to a smoothing capacitor 12. Also, connected between both terminals of load 13 is an output voltage detector 18 which comprises an error amplifier 14, a normal power supply 15 for providing a reference voltage for an inverted input terminal of error amplifier 14, and a photocoupler 16 driven by an output from error amplifier 14. Non-inverted terminal of error amplifier 14 is connected to positive terminal of load 13, and output terminal of error amplifier 14 is connected to an anode terminal of a light emitting diode (light emitter) 16a of photocoupler 16 whose cathode terminal is connected to negative terminal of load 13. Positive and negative terminals of normal power supply 15 are connected to inverted terminal of error amplifier 14 and negative terminal of load 13. A light receiving or photo-transistor (light receiver) 16b of photocoupler 16 receives a light from light emitting diode 16a, and both terminals of photo-transistor 16b are connected to associated input terminals 2a and 2b of control circuit 2. Both terminals of a regulatory capacitor 30 are connected to control terminals 2c and 2d of control circuit 2 to adjust a resonance frequency.
FIGS. 2 and 3 indicate voltage and current waveforms at selected locations in the circuit shown in FIG. 1 during the light and full load periods. FIG. 4 shows voltage and current waveforms occurring for long cycles wherein symbols Vg1 and Vg2 denote respectively time charts of switching or drive signals applied to control or gate terminals of first and second MOS-FETs 3 and 4. Switching signals from control circuit 2 are intermittent pulse signals which each involves a constant dead time.
In operation of the switching power source device shown in FIG. 1, when control circuit 2 forwards a drive signal Vg1 to gate terminal of first MOS-FET 3 while second MOS-FET 4 is in the off-condition, first MOS-FET 3 is turned on so that resonant current I1 flows from power source 1 through first MOS-FET 3, resonance reactor 7, primary winding 9a of transformer 9 and resonance capacitor 8 for resonance of reactor 7 and capacitor 8, thereby causing resonance current I1 to increase voltage applied on primary winding 9a of transformer 9.
Resonance current I1 produces and increases an induced voltage applied on first secondary winding 9b of transformer 9. When induced voltage is elevated up to a threshold level of DC output voltage VOUT, it is clamped with DC output voltage level VOUT to generate through rectifying diode 10 an output current which charges output smoothing capacitor 12 and at the same time supplies DC electric power to load 13. Then, voltage on primary winding 9a starts to decease, thereby lowering induced voltage on first secondary winding 9b. When induced voltage drops below threshold level of DC output voltage VOUT, no electric power is supplied to the secondary side of transformer 9 so that resonance current I1 flows through first MOS-FET 3, resonance reactor 7, primary winding 9a and resonance capacitor 8 with low frequency determined by resonance reactor 7, primary winding 9a and resonance capacitor 8 to accumulate energy in resonance reactor 7, primary winding 9a and resonance capacitor 8. Symbol VC2 denotes a voltage across resonance capacitor 8.
Subsequently, when first MOS-FET 3 is turned off, voltage resonance appears on voltage resonance capacitor 6 by a serial circuit which comprises resonance reactor 7, primary winding 9a and resonance capacitor 8 plus voltage resonance capacitor 6. Applied voltage VC1 across voltage resonance capacitor 6 varies through a part of voltage resonance sine waveform between power source voltage VIN and ground level, thereby likewise varying voltages applied on secondary windings 9b and 9c. When voltage VC1 across voltage resonance capacitor 6 is lowered from power source voltage VIN to ground level, but before comes to negative voltage, parasitic diode 4a of second MOS-FET 4 becomes conductive to clamp voltage VC1 across voltage resonance capacitor 6 at ground level so that resonance current I2 flows through the primary circuit of transformer 9 for resonance by reactor 7 and capacitor 8. During the conductive period of parasitic diode 4a, namely during the clamped period of voltage VC1 across voltage resonance capacitor 6 at ground level, more specifically during the zero voltage period of second MOS-FET 4, switching signal Vg2 is applied to gate terminal of second MOS-FET 4 to turn second MOS-FET 4 on for zero voltage switching.
While second MOS-FET 4 is turned on after voltage applied on secondary windings 9b and 9c of transformer is changed for polarity inversion, secondary current flows from second secondary winding 9c of transformer 9 through parallel rectifying diode 11 to charge output smoothing capacitor 12 and supply DC electric power to load 13. When voltage across second secondary winding 9c drops and comes below threshold of DC output voltage VOUT, power supply to secondary side of transformer 9 ceases. On the other hand, primary side of transformer 9 provides a current resonance circuit of resonance reactor 7, primary winding 9a, resonance capacitor 8 and second MOS-FET 4 to cause current resonance with its low frequency and thereby accumulate energy in resonance reactor 7, primary winding 9a and resonance capacitor 8.
After that, when second MOS-FET 4 is turned off under the off-condition of first MOS-FET 3, voltage resonance occurs on capacitor 6 by series circuit of resonance reactor 7, primary winding 9a and resonance capacitor 8 plus voltage resonance capacitor 6 so that voltage resonance causes voltage VC1 across capacitor 6 to increase from ground level toward power source voltage VIN along a part of voltage resonance sine waveform. Simultaneously, voltage on secondary windings 9b and 9c similarly changes. When voltage VC1 reaches power source voltage VIN, parasitic diode 3a of first MOS-FET 3 becomes conductive to clamp voltage VC1 at the power source voltage VIN. When a switching signal Vg1 is applied to gate terminal of first MOS-FET 3 during the clamped period of voltage VC1 and the conductive period of parasitic diode 3a, namely during the zero voltage period of first MOS-FET 3, it is turned on for zero voltage switching.
Repetition of the foregoing operation causes first and second MOS-FETs 3 and 4 to be alternately turned on and off with the duty ratio of approximately 50%.
Output voltage detector 18 picks out DC output voltage VOUT supplied to load 13 to produce a detection signal to control circuit 2 through photocoupler 16. Error amplifier 14 compares output voltage VOUT to load 13 with reference voltage from normal power supply 15 to produce error signal, the difference between output voltage VOUT and reference voltage. Accordingly, with higher output voltage VOUT than reference voltage, error amplifier 14 generates greater output current transmitted through photocoupler 16 to control circuit 2 which provides switching signals of narrower on-pulse to first and second MOS-FETs 3 and 4. Adversely, with lower output voltage VOUT than reference voltage, error amplifier 14 generates smaller output current transmitted through photocoupler 16 to control circuit 2 which provides switching signals of wider on-pulse to first and second MOS-FETs 3 and 4. In this way, control circuit 2 serves to control and adjust output voltage VOUT toward a constant level. The embodiment shown in FIG. 1 can utilize switching signals Vg1 and Vg2 inclusive of a constant dead time and of variable on-span of switching signal for switching frequency control. Such a switching power source device of resonance type can reduce and heighten the switching frequency respectively during the full and light load periods as shown in FIG. 5. To this end, control circuit 2 modulates pulse frequency (PFM, Pulse Frequency Modulation) of switching signals Vg1 and Vg2 to gate terminals of first and second MOS-FETs 3 and 4 in response to detection signals from output voltage detector 18 to control the on-off operation of first and second MOS-FETs 3 and 4 in order to stabilize DC output voltage VOUT.
FIG. 6 exhibits an example of control circuit 2 wherein control terminal 2a connects a first current regulator 31b of a charging circuit 31 with photo-transistor 16. A positive terminal of first current regulator 31b is connected to DC power source through a first switch 31a, and a negative terminal of first current regulator 31b is connected to a junction. A discharging circuit 32 comprises a second switch 32a and a second current regulator 32b connected in series to each other between a junction and ground. Also, a junction is connected to regulatory capacitor 30 through control terminal 2c and to one input terminal of a comparator 33 which has the hysteretic characteristics capable of producing two thresholds VH and VL of high and low voltage levels. An output terminal of comparator 33 is connected to an inverter 34 and second switch 32a through b junction. An output terminal of inverter 34 is connected to T input terminal of a T flip flop (TFF) 35, first switch 31a and each one input terminal of AND gates 36 and 37. A Q output terminal of TFF 35 is connected to the other input terminal of AND gate 36, and a Q bar output terminal of TFF 35 is connected to the other input terminal of AND gate 37. Output terminals of AND gates 36 and 37 are connected respectively to each one input terminal of AND gates 40 and 41. Each of the other input terminals of AND gates 40 and 41 is connected to an output terminal of error amplifier 42 which has a non-inverted input terminal connected to a junction of a capacitor 44 and a resistor 48, and an inverted input terminal connected to a normal power supply 43 for generating a reference voltage. A series circuit of resistor 43 and capacitor 44 is connected between DC power source and ground.
In operation of control circuit 2, when inverter 34 produces its output of high voltage level, first switch 31a of charging circuit 31 is turned on to charge regulatory capacitor 30 by charge current flowing through first switch 31a and first current regulator 31b. Charged level of regulatory capacitor 30 determines the switching rate of TFF 35, namely resonance frequency of current I1 flowing resonance capacitor 8, first current regulator 31b produces a controlled constant current value to provide charge time constant for regulatory capacitor 30, and photo-transistor 16b controls the value of current passing through current regulator 31b. When regulatory capacitor 30 is charged up to high voltage threshold VH from comparator 33, comparator 33 changes the output to high voltage level which triggers to turn second switch 32a on, and therefore, discharge current flows from regulatory capacitor 30 through second switch 32a and second current regulator 32b to discharge regulatory capacitor 30, while concurrently inverter 34 produces its output of low voltage level to turn off charging circuit 31 and AND gate 36. Second current regulator 32b provides discharge time constant of discharge current running therethrough. When regulatory capacitor 30 is discharged to low voltage threshold VL from comparator 33 which then changes the output to low voltage level, second switch 32a is turned off, and at the same time, first switch 31 is turned on. In this way, comparator 33 alternately changes the output between high and low voltage levels in response to charged and discharged levels of regulatory capacitor 30, repeating these operations.
Comparator 33 produces its output which is then inverted by inverter 34, and TFF 35 alternately switches the output level from Q and Q bar output terminals each time rising edge of inverted signals from inverter 34 is supplied to T input terminal of TFF 35. In detail, when inverter 34 offers a first high voltage level signal to T input terminal, TFF 35 produces the output from Q output terminal in response to first high voltage level signal from inverter 34 without producing the output from Q bar output terminal. Therefore, receiving the output from Q terminal of TFF 35 and the signal from inverter 34, AND gate 36 is turned on to produce the output to AND gate 40 which provides switching signal Vg1 to first MOS-FET 3 when error amplifier 42 generates the output of high voltage level.
Afterward, when inverter 34 has changed the output to low voltage level, AND gate 36 shifts to switch the output signal to low voltage level to provide a dead time period. Then, when inverter 34 again produces the output of high voltage level, TFF 35 changes the output from Q terminal to low voltage level, and simultaneously the output from Q bar terminal to high voltage level. Thereby, AND gates 36 and 37 change their outputs respectively to low and high voltage levels, so AND gate 41 produces the output of high voltage level to give second MOS-FET 4 a switching signal Vg2. After that, when inverter 34 changes the output to low voltage level, AND gate 37 shifts the output to low voltage level to provide a dead time period. Thus, AND gates 36 and 37 serve to add a dead time to each of switching signals Vg1 and Vg2 for first and second MOS-FETs 3 and 4.
Charge and discharge voltages on regulatory capacitor 30 form the triangular waveform with time course, and during the increasing ramp period of charge voltage on regulatory capacitor 30, either of first and second MOS-FETs 3 and 4 is in the on-condition, and during the decreasing ramp period of discharge voltage on regulatory capacitor 30, both of first and second MOS-FETs 3 and 4 are in the off-condition. Controlling current flow passing through first and second current regulators 31b and 32b enables adjustment of respectively current charge and discharge amount or rate to and from regulatory capacitor 30.
As mentioned above, resonant switching power source device for frequency control requires adjustment of output power by increasing oscillation frequency during the light load period to stabilize the output voltage to a constant level, thereby causing switching elements to make them operate with the high switching frequency. This results in increase in switching energy loss by control circuit or MOS-FETs as switching elements, and therefore the power source device is disadvantageous in that it has the lower energy conversion efficiency during the light load period than those of switching power sources of other type for driving switching elements with unchanged frequency. To resolve this problem, Japanese Patent Disclosure No. 8-130871 proposes a switching power source device. As shown in FIG. 6, the disclosed device has an additional input terminal 61 connected to non-inverted input terminal of error amplifier 42, capacitor 44 and resistor 48 to apply switching signals to additional input terminal 61 so that both of two switching elements for high and low sides are coincidentally turned off to provide the pause periods between two pulses of voltage VC1 shown in FIG. 7 and intermittent operation for switching elements.
This device, however, is still defective in that it incurs the switching loss and noise during the non-resonance or dissonance operation resulted from the pause period.
An object of the present invention is to provide a switching power source device capable of controlling switching loss and noise by reducing or preventing non-resonance operation at the time of lowered switching frequency to thereby improve energy conversion efficiency during the light load period.